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ISTC-CC Abstract
Fast Bulk Bitwise AND and OR in DRAM.
IEEE Computer Architecture Letters (CAL), April 2015..
Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee,
Michael A. Kozuch*, Onur Mutlu, Phillip B. Gibbons*, Todd C. Mowry
Carnegie Mellon University
* Intel Pittsburgh
Bitwise operations are an important component of modern day programming, and are used in a variety of applications such as databases. In this work, we propose a new and simple mechanism to implement bulk bitwise AND and OR operations in DRAM, which is faster and more efficient than existing mechanisms. Our mechanism exploits existing DRAM operation to perform a bitwise AND/OR of two DRAM rows completely within DRAM. The key idea is to simultaneously connect three cells to a bitline before the sense-amplification. By controlling the value of one of the cells, the sense amplifier forces the bitline to the bitwise AND or bitwise OR of the values of the other two cells. Our approach can improve the throughput of bulk bitwise AND/OR operations by 9.7X and reduce their energy consumption by 50.5X. Since our approach exploits existing DRAM operation as much as possible, it requires negligible changes to DRAM logic. We evaluate our approach using a real-world implementation of a bit-vector based index for databases. Our mechanism improves the performance of commonly-used range queries by 30% on average.
FULL PAPER: pdf
