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ISTC-CC Abstract
A Heterogeneous Multiple Network-on-Chip Design: An Application-Aware Approach
Proceedings of the 50th Design Automation Conference (DAC), Austin, TX, June 2013.
Asit K. Mishra*, Onur Mutlu, Chita R. Das**
Carnegie Mellon University
*Intel Labs
**The Pennsylvania State University
Current network-on-chip designs in chip-multiprocessors are agnostic to application requirements and hence are provisioned for the general case, leading to wasted energy and performance. We observe that applications can generally be classified as either network bandwidth-sensitive or latency-sensitive. We propose the use of two separate networks on chip, where one network is optimized for bandwidth and the other for latency, and the steering of applications to the appropriate network. We further observe that not all bandwidth (latency) sensitive applications are equally sensitive to network bandwidth (latency). Hence, within each network, we prioritize packets based on the relative sensitivity of the applications they belong to. We introduce two metrics, network episode height and length, as proxies to estimate bandwidth and latency sensitivity, to classify and rank applications. Our evaluations show that the resulting heterogeneous two-network design can provide significant energy savings and performance improvements across a variety of workloads compared to a single one-size-fits-all single network and homogeneous multiple networks.
FULL PAPER: pdf
