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ISTC-CC Abstract
Error Patterns in MLC NAND Flash Memory:
Measurement, Characterization, and Analysis
Design, Automation, and Test in Europe Conference (DATE), March 12-16, 2012, Dresden, Germany.
Yu Cai*, Erich F. Haratsch^, Onur Mutlu* and Ken Mai*
*Electrical and Computer Engineering, Carnegie Mellon University
^LSI Corporation, 1110 American Parkway NE, Allentown, PA
As NAND flash memory manufacturers scale down to smaller process technology nodes and store more bits per cell, reliability and endurance of flash memory reduce. Wear-leveling and error correction coding can improve both reliability and endurance, but finding effective algorithms requires a strong understanding of flash memory error patterns. To enable such understanding, we have designed and implemented a framework for fast and accurate characterization of flash memory throughout its lifetime. This paper examines the complex flash errors that occur at 30-40nm flash technologies. We demonstrate distinct error patterns, such as cycle-dependency, locationdependency and value-dependency, for various types of flash operations. We analyze the discovered error patterns and explain why they exist from a circuit and device standpoint. Our hope is that the understanding developed from this characterization serves as a building block for new error tolerance algorithms for flash memory.
KEYWORDS: NAND flash; error patterns; endurance; reliability; error correction
FULL PAPER: pdf