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ISTC-CC Abstract
Parallel Application Memory Scheduling
The 44th International Symposium on Microarchitecture, Porto Alegre, Brazil, December 2011.
Eiman Ebrahimi†, Rustam Miftakhutdinov†, Chris Fallin§, Chang Joo Lee‡,
José A. Joao†, Onur Mutlu§, Yale N. Patt†
†University of Texas at Austin
§Carnegie Mellon University
‡Intel Corporation
A primary use of chip-multiprocessor (CMP) systems is to speed up a single application by exploiting thread-level par- allelism. In such systems, threads may slow each other down by issuing memory requests that interfere in the shared memory subsystem. This inter-thread memory system in- terference can significantly degrade parallel application performance. Better memory request scheduling may mitigate such performance degradation. However, previously proposed memory scheduling algorithms for CMPs are designed for multi-programmed workloads where each core runs an in- dependent application, and thus do not take into account the inter-dependent nature of threads in a parallel application.
In this paper, we propose a memory scheduling algorithm designed specifically for parallel applications. Our approach has two main components, targeting two common synchronization primitives that cause inter-dependence of threads: locks and barriers. First, the runtime system esti- mates threads holding the locks that cause the most serialization as the set of limiter threads, which are prioritized by the memory scheduler. Second, the memory scheduler shuffles thread priorities to reduce the time threads take to reach the barrier.We show that our memory scheduler speeds up a set of memory-intensive parallel applications by 12.6% com- pared to the best previous memory scheduling technique.
KEYWORDS: Parallel Applications, Shared Resources, CMP, Memory Controller, Multi-core, Memory Interference.
FULL PAPER: pdf