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ISTC-CC Abstract
SHiP: Signature-Based Hit Predictor for High
Performance Caching
The 44th Annual IEEE/ACM International Symposium on Microarchitecture, December 2011.
Carole-Jean Wu, Aamer Jaleel†, William Hasenplaugh†‡, Margaret Martonosi,
Simon Steely Jr.†, Joel Emer†‡
Princeton University
†Intel Corporation, VSSAD
‡Massachusetts Institute of Technology
The shared last-level caches in CMPs play an important role in improving application performance and reducing off-chip memory bandwidth requirements. In order to use LLCs more efficiently, recent research has shown that changing the re-reference prediction on cache insertions and cache hits can significantly improve cache performance. A fundamental challenge, however, is how to best predict the re-reference pattern of an incoming cache line. This paper shows that cache performance can be improved by correlating the re-reference behavior of a cache line with a unique signature. We investigate the use of memory region, program counter, and instruction sequence history based signatures. We also propose a novel Signature-based Hit Predictor (SHiP) to learn the re-reference behavior of cache lines belonging to each signature. Overall, we find that SHiP offers substantial improvements over the baseline LRU replacement and state-of-the-art replacement policy proposals. On average, SHiP improves sequential and multiprogrammed application performance by roughly 10% and 12% over LRU replacement, respectively. Compared to recent replacement policy proposals such as Seg-LRU and SDBP, SHiP nearly doubles the performance gains while requiring less hardware overhead.
KEYWORDS: Replacement, Reuse Distance Prediction, Shared Cache
FULL PAPER: pdf
